Imaging devices implemented in complementary metal oxide semiconductor (CMOS) are well known and widely used together with CCD image sensors. CMOS imaging devices have a number of advantages: (1) they can reduce the cost and power consumption, (2) they are easy to manufacture, employing the highly standardized process developed for massive production of consumer integrated circuits (ICs) including memory chips and microprocessors and other digital and analog ICs, and (3) they integrate multiple functions on a single chip, allowing the scaling down of the size and power consumption of the device. They also allow for the adoption of smaller geometry processes provided by new advancements in the CMOS process.
Imaging devices are typically formed from rows and columns of pixels which include photo-detecting devices and supporting circuits. The photo-detecting devices typically include photodiodes, photoconductors, and photocapacitors, each of which may generate photo-charges in proportional to the photons impinging on the photodetectors. A CMOS pixel typically includes a photodiode, and three or four transistors that convert the photo-charges to voltage signal for the pixel output.
Typically, the one or more photodetectors in the pixel array receives only a fraction of light flux falling on the entire pixel area. This is because the pixel includes supporting circuitry that blocks the incoming light and typically does not function as a photodetector. The percentage of the photodetector area to the pixel area is often referred to as the optical fill factor. Typically, the fill factor of a small pixel is less than 30%. This means that less than 30% of the light energy received by the pixel is detected by the one or more photodetectors in the pixel.
A microlens system, which needs additional fabrication processing, is typically placed over every pixel in the pixel array to enhance the fill factor by focusing the light beam on the photodetector. This approach generally requires a gap of typically 0.7 μm between each microlenses due to fabrication requirements. For a small pixel on the order of 2 μm×2 μm, the microlens has a circular shape with an approximate diameter of 1.3 μm. In this case, a microlens is only able to cover about 33% of the pixel area. Consequently, enhancement of the fill factor by using a microlens is negligibly small for the small CMOS pixel case.
Furthermore, light needs to penetrate through multiple thick dielectric layers until it reaches down to the surface of the photodetector. (FIG. 1). At each interface between adjacent layers, some of the light is reflected due to the refractive index variations and the presence of an interface. Further, light energy is lost during transmission through the thick layers. This light transmission loss is proportional to the number of layers and the thickness of the layers. Further, multiple dielectric layers are formed due to CMOS fabrication requirements. Modern CMOS processes typically employ 5 to 6 metal layers for image sensor fabrication. This leads to depositions of 5 μm to 6 μm thick dielectric layers as each dielectric layer and metal layer is approximately 1.0 μm thick. Further, on top of the photodetector, where no metal layers are present, the dielectric layers are coated with a planarization layer for the planarization of the surface layer.
As a result, light energy loss due to transmission loss may become significant. In addition, when the pixel size is as small as 2.0 μm×2.0 μm or even smaller, the aspect ratio of the height to the size of the window opening of the metal layers above the photodetector is greater than 6. In this case, light beams can be blocked by the metal layers when light is incident at an angle other than perpendicular to the imaging plane. If a microlens is employed, the aspect ratio becomes even higher and results in a worse light shadow effect. This light shadowing becomes worsened as the pixel size becomes smaller. Consequently, the pixel signal is severely reduced, resulting in an unacceptable signal to noise ratio SNR.
Accordingly, there is a need to overcome these issues by introducing a new type of pixel architecture. Preferably, the new architecture should be CMOS compatible for ease of manufacture and electronics integration.